The present disclosure relates to an analog-to-digital (A/D) converter that converts an analog signal into a digital signal at high speed and also relates to a signal processing system.
As systems best suited for analog-to-digital (A/D) conversion at high speed, parallel A/D conversion and serial-parallel A/D conversion have been known.
For conversion of an analog input signal (voltage) into an N-bit digital signal, parallel A/D converters have a reference circuit that supplies an N-bit reference voltage and a comparator group that compares the reference voltage supplied from the reference circuit with the analog input signal.
In addition, the parallel A/D converters have an encode unit that converts an analog signal into a digital signal and a timing generator that controls the whole timing.
Serial-parallel A/D converters basically have a multiplexer composed of a switch group besides a parallel A/D converter.
Meanwhile, as serial-parallel A/D converters, sub-ranging A/D converters having a coarse A/D converter (CADC) and a fine A/D converter (FADC) have been known. In the sub-ranging A/D converters, A/D conversion is first coarsely performed by the CADC and then finely performed by the FADC.
FIG. 1 is a diagram showing a configuration example of the TH circuits of the coarse A/D converter and the fine A/D converter of a sub-ranging A/D converter.
At the input stage of a coarse A/D converter (CADC) 11C, a track-and-hold (TH) circuit 12C for the CADC is disposed. At the input stage of a fine A/D converter (FADC) 11F, a TH circuit 12F for the FADC is disposed.
The coarse A/D converter 11C includes an amplifier AMP11C and a quantization circuit (binarization circuit) QUA11C. The fine A/D converter 11F includes an amplifier AMP11F and a quantization circuit (binarization circuit) QUA11F.
The TH circuit 12C for the CADC includes switches SW1C to SW5C and a sampling capacitor CsC.
The switch SW1C has its terminal a connected to the supply line for a voltage VC1 and its terminal b connected to the terminal a of the switch SW5C and one end (first electrode) of the sampling capacitor CsC.
The switch SW2C has its terminal a connected to the supply line for an analog input signal vin and its terminal b connected to the other end (second electrode) of the sampling capacitor CsC.
The switch SW3C has its terminal a connected to the supply line for a coarse reference voltage VREFC supplied from a reference circuit (not shown) and its terminal b connected to the other end (second electrode) of the sampling capacitor CsC.
The switch SW4C has its terminal a connected to the supply line for a voltage VC4 and its terminal b connected to the terminal b of the switch SW5C and the input of the coarse A/D converter 11C.
It should be noted that the reference circuit is composed of a resistor ladder including a plurality of resistors R connected in series between a power supply VRT on a high potential side and a power supply VRB on a low potential side.
In the TH circuit 12C for the CADC, the analog input signal vin is sampled when only the switches SW1C, SW2C, and SW4C are turned on.
Then, a comparison voltage compared with the coarse reference voltage VREFC is supplied from the reference circuit to the amplifier AMP11C of the subsequent coarse A/D converter 11C when only the switches SW3C and SW5C are turned on.
The TH circuit 12F for the FADC includes switches SW1F to SW5F and a sampling capacitor CsF.
The switch SW1F has its terminal a connected to the supply line for the voltage VC1 and its terminal b connected to the terminal a of the switch SW5C and one end (first electrode) of the sampling capacitor CsF.
The switch SW2F has its terminal a connected to the supply line for the analog input signal vin and its terminal b connected to the other end (second electrode) of the sampling capacitor CsF.
The switch SW3F has its terminal a connected to the supply line for a fine reference voltage VREFF selected by a multiplexer (not shown) with the output of the coarse A/D converter 11C and its terminal b connected to the other end (second electrode) of the sampling capacitor CsF.
The switch SW4F has its terminal a connected to the supply line for the voltage VC4 and its terminal b connected to the terminal b of the switch SW5F and the input of the fine A/D converter 11F.
In the TH circuit 12F for the FADC, the analog input signal vin is sampled when only the switches SW1F, SW2F, and SW4F are turned on.
Then, the comparison voltage compared with the fine reference voltage VREFF is supplied to the amplifier AMP11F of the subsequent fine A/D converter 11F when only the switches SW3F and SW5F are turned on.